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Asynchronous Design
Introduction
Digital designs can be divided into synchronous and asynchronous
circuits. The common timing reference called clock signal defined the
synchronous designs. Consequently, asynchronous designs are those
without a common timing reference. In the early days of digital
design, design methodologies were not established and combinations of
synchronous and asynchronous techniques were used. From the 1960s to
the present, the usage and the development of synchronous circuits and
methods has achieved almost total dominans. When computers were first
constructed, a few of them were fully asynchronous. Two examples are
ORDVAC from the University of Illinois (1951-52) and later, MU5 from
the University of Manchester (1969-74). But asynchronous techniqus
have later found their applications in places where synchronous
techniques are not feasible. A typical example is high-speed
communication over long distances, such in computer bus systems.
UNIBUS in PDP-11 (1969) and VMEBUS (1980) are examples of such
asynchronous buses.
The growing complexity of ICs makes clock distribution in
synchronous designs more costly to design in terms of power
consumption, area, and design effort. The clock distribution problem
has made asynchronous design techniques a viable alternative. Some of
the research carried out in the field of asynchronous design searches
for ways to utilize these advantages for solving real-world problems.
Most of the work in this area is carried out at universities, but
there is also some research in industry. For example, Sun Micro
Systems Labs proposed a new processor architecture called Counterflow
Pipeline Processor and Philips Research Labs has focused on designing
low-power ICs using automatic synthesis of asynchronous circuits. In
recent years a mixed synchronous/asynchronous approach, called
Globally Asynchronous - Locally Synchronous (GALS), has been
advocated. The basic idea is to have a local clock for for each module
on the chip and to have asynchronous communication between the
synchronous modules. When considering other complex digital systems
based on multiple ICs and PCBs, this seems to be a natural development
for very complex ICs.
Motivation
Asynchronous design methods differ significantly from the methods
that are currently used. Shifting methods is a large step and requires
substantial motivation. The main motives found in litterature for
using asynchronous techniques are ilsted below
 | Average case performance
In synchronous systems, the slowest combinational path defines the
maximum clock frequency. This leads to worst-case performance for
all operations independently on the data. Asynchronous data-paths
are designed to indicate when computation is completed. The
computation time for many operations is very data dependent and
this property can be exploited in cases where the worst-case delay
is much larger than the average delay. |
| No clock skew problems
In a asynchronous system, the differences in arrival time of the
clock signal to different parts of the system must be controlled.
Clock skew affects speed performance and may also cause
malfunctioning due to race conditions. The cost of maintaining low
clock skew becomes higher when the complexity of the IC increases.
Asynchronous circuits do not have a global clock signal and clock
skew is therefore not a problem. |
| Low power consumption
Only active parts of a CMOS design dissipates power in CMOS (for
how long will this be true ...). In a synchronous system, the
clock signal is still active in the idle parts. The event-driven
nature of asynchronous designs leads to the fact that only the
parts of the design that actually take part in the computation are
dissipating power. |
| Low noise
Simultanous switching in CMOS leads to high current transitions in
the power lines. In a synchronous system, the charge and discharge
of the clock net is a large contributor to the current
transitions. Most of the switching in the gates occurs shortly
after the active clock edge. This makes the total current
concentrated to the time of the active clock edge. The fast
current transitions cause fluctuations on the power supply lines
that may cause lowered speed performance or malfunctioning of the
digital logic. In a mixed analog/digital system, the digital noise
will affect the sensitive analog circuits. Asynchronous circuits
are not synchronized and the cirrent is more uniformly distributed
in time. |
| Modularity
In an asynchronous module, both timing and functionality are
located inside the module. From the user's point of view, only the
sequency of operations is important when using the module.
Incremental upgrading of the performance of the asynchronous
system only requires the replacement of the module that is
limiting the performance, without having to change or retime the
system in any other way. |
| Scalability
In general, a digital system consists of different parts
mplemented in different technologies and these communicate over
different types of media. Different types of design techniques are
then used for different types of implementation technologies. A
typical scenario is as follows: Inside the IC, a high-speed global
clock signal is used that is generated from a PLL, which is
synchronized to a slower external clock signal. Communication
between the ICs on the same PCB is synchronized to the slower
clock. Board-to-board communication is handled by an asynchronous
standard bus system (such as VMEBUS). Crossing the boarders of
implementation technologies makes it necessary to introduce new
design techniques. By using asynchronous circuits from the
beginning, it is possible to keep the same design technique
throughout the system design. |
Our work
Our work on fully asynchronous design has been directed towards
investigations in complex IC design using micropipeline structures.
The first work we made, studied the design and implementation of a
macro-cell library for designing fully asynchronous ICs. The approach
to macro-cell design has been to base the cells on generic
micropipeline structures, one for pipelines and one for feedbacks. The
micropipeline technique has been selected because of its similarities
to synchronous circuits when it comes to performance and synthesis
methods. The generic structures have been designed so that the control
path is kept simple in order to keep the overall delay small.
The macro-cell library has been used for designing a fairly complex
DSP IC containing approximately 100,000 transistors. The IC is a DSP
for a high data-rate spread-spectrum digital receiver. The peak
sampling rate was measured to 48 MSamples/s at 5V power supply
voltage. The IC was found work correctly from 1.5V to 5V power supply
voltages.
Some of the papers we published that are related to this design:
- Bengt Oelmann and Hannu Tenhunen, "A system level
performance model for asynchronous micropipeline circuits,"
in Proceedings of the 13th IEEE International Conference on
Electronics, Circuits, and Systems, Rodos, Greece, October
1996, pp. 952-955.
- Bengt Oelmann and Hannu Tenhunen, "Comparison of self-timed
and synchronous high-speed VLSI/ULSI circuits using system level
performance modelling," poster presentation at GHz-conference,
1995, Gothenburg, Sweden.
- Bengt Oelmann, Henk Martijn, and Hannu Tenhunen, "Design of
an asynchronous macro-cell library," in Proceedings of
the 13th Norchip Conference, Copenhagen, Denmark, November
1995, pp. 185-193.
- Bengt Oelmann and Hannu Tenhunen, "Micropipeline DSP-ASIC
for DS-SS receiver," in Proceedings of the 1996 Ninth
Annual IEEE International ASIC Conference, Rochester, NY,
USA, September, 1996, pp. 227-230.
- Bengt Oelmann, Henk Martijn, and Hannu Tenhunen, "An
asynchronous implementation of a DS-SS radio receiver," in Proceedings
of the 6th IEEE Conference on Personal Indoor Radio Communication,
September 1995, Toronto, Canada, pp. 1252-1256.
- Bengt Oelmann, Henk Martijn, and Hannu Tenhunen, "Design of
an asynchronous direct sequence spread spectrum digital radio
receiver," in Proceedings of the Nordic Radio Symposium,
1995, Stockholm, Sweden.
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| Fully
asynchronous DSP-ASIC |
| Our fully asynchronous DSP for
high data-rate spread-spectrum communication.
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