LIFS stands for Low-Power Implementation of Finite State Machines. This is the project name and also the name of the synthesis tool that is the result of this project.
 | Background The most common way to reduce average power consumption in Finite-State Machines (FSMs) is to partition them into several sub-FSMs. The power consumption can be reduced by only having one of the smaller sub-FSM active at a time. Strongly connected states (there is a high probability of having state transitions among these) are clustered at put in the same sub-FSM. |
| Our Approach There is a cost, in terms of power consumption, to partition a FSM to several sub-FSMs. Extra circuitry is introduced to handle the communication between the sub-FSMs. The previously existing techniques used synchronous handling of this communication protocol. We have recognized that the power consumption can be reduced when using an asynchronous communication protocol. The power reduction is due to: (1) extra capacitance introduced on the global clock is minimized, (2) A more power efficient communiaction protocol can be used. |
| Results The new synthesis procedures have been implemented in a prototype tool that takes a FSM description in a State Transition Graph format and generates a partitioned FSM optimized for low power consumption. The output of the tool is synthesizable RT-level VHDL. We have used a set the standard MCNC benchmarks and found that an average power reduction of 46% was obtained. |
| Future work We intend to extend to tool for optimizing for lowering the maximum power consumption. The motivation is to get circuits that have low dI/dt in order to reduce the noise on the power lines. |