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Imran Muhammad |
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This page contains projects that I supervised and the projects that I was personally involved. |
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This project aimed at investigation of low power wireless smart camera on an embedded software platform for detection of magnetic particles in hydraulic machine’s oil and report the error to the user wirelessly . See project detail [link] |
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In this project vision algorithms are developed in VHDL for hardware implementation and then Sensor node is implemented on hardware platform. The Sensor node include ACTEL, Xilinx FPGA, AVR32 Micro-controller and CC2520 chipcon transceiver. The proposed architecture has low energy to achieve a life time of 5 years for specific application on 4 AA batteries. See project [link] publication [link] |
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In this project CCITT group4 compression Algorithm compression is first implemented in MATLAB and C. After this, the compression scheme is implemented in VHDL for hardware implementation. The functionality is verified on ACTEL and Xilinx FPGA. The compression performance for different set of images is 455 bytes on the average with standard deviation of 166 bytes. You can download input set of images and see the hardware design in case you want to perform similar experiment. [Hardware design flow]
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Magnetic Particles Detection System on an Embedded Software Platform. |
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CCITT group4 software and hardware implementation |
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Implementation Smart camera Node |
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Project List |
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In this work, we have investigated different bi-level compression schemes including JBIG2, CCITT group3, group4, GZIP, GZIP pack, rectangular on resource constrained environment. The bi-level compression is selected because in WVSN system, lightweight algorithms are used for reducing data for transmission. The two compression schemes, CCITT group4 and JBIG2 were candidates for hardware platform. It was concluded that JBIG2 cost more in terms of resources (memory and logic) and design efforts than the performance it offers. Therefore CCITT group4 was chosen for software and hardware implementation. [Input images], [ paper ].
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Bi-level compression on hardware platform |
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Eagle detection project [ slide show] [ video] [ motivation] |
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Wireless modules |
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In this project vision algorithm for extracting changes in the field of view is developed. The algorithms is implemented in VHDL and functionality is tested on FPGA for hardware implementation. See design flow detail. |
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Change coding for vision systems |
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We a group of two students in the course Design of Embedded DSP Processor have designed and implemented a small DSP processor in VHDL. The processor could perform arithmetic operation like addition, subtraction and other basic operations like saturation, finding maximum, minimum in two numbers. It also includes controlling of simple as well as complex instructions like conditional and unconditional jump. |
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Design and Implementation of a small DSP processor in VHDL. |
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We a group of two students in Low Power Electronic course designed a 16-bit High Speed Multiplier for Low Power with a throughput of 100Msamples/sec. Main Tasks were to introduce Pipelining and Interleaving to get extra time margin which was traded for voltage scaling resulting in low power consumption. The functionality was verified in ModelSim, Area and propagation delay was estimated in design Analyzer and Power consumption was estimated in nanosim. |
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Designing of a High Speed Multiplier for Low Power. . |
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The project included methods and tools for the design and implementation of complex electronic systems. The goal of this project was to design an FPGA based system which takes analog audio input, converting it into the digital form, after processing in FPGA the result is to be displayed on a attached VGA screen or played on a loud speaker. |
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Design of a Stereo Sound Processing System. |
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The project included complete design flow, from Chip design to Tape Out. It included behavioral, schematic, layout level simulations and chip testing. I was the team leader and responsible for implementation of ADC and integration. The project included LIPS model for documentation in order to promote teamwork and communication skills necessary for successful complex VLSI projects. |
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VLSI Design & Implementation of Sigma-Delta ADC in 0.35μm technology. |
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Sigma Delta Modulator Chip |
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Remote meter reading project |
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Graphical User Interface for of Wireless Vision Sensor Node |
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Currently, (June 2013), I am working on RTL modeling of FLASH memory controller. This will enable to erase, write and read the FLASH with downscaled version of an image. documentation |
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FLASH controller with up/down scaled image on FPGA. |
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Vision processing is performed on SRAM based FPGA. Compressed ROI data is transmitted over a IEEE 802.15.4 compliant transceiver which is being controlled by AVR32 microcontroller. A user friendly GUI controls the smart camera. video. |
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Energy Efficient and Programmable FPGA based wireless smart Camera |
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Particle detection Remote meter Bird detection People counting |
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Test cases |
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Student Projects I feel pleasure to work with students on challenging projects. Some of the completed projects that I supervised are listed here.
· Evaluating the effect of different distances on the pixels per object and image classification, Amiryousef Samaei. · tudy of High Level Synthesis Tool Generated RTL vs Designer Written RTL for Vision Functions [ link ], Sandeep kumar Chetty. · Camera Node for Conical Volumetric Surveillance, zhennan zhang [ link ] · Background Subtraction for FPGA based Thermal Smart Camera System, Huma Munir. [ publication ] [ publication] · A user friendly interface for smart camera by using Qt and image processing on the server by using OpenCV, Jagan mohan Krishna raj |
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Projects that I was involved in This section includes small and big projects that I was personally involved in |
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Autonomous monitoring system for rail tracks |
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muhammad.imran@miun.se |